Business News Holding

Tag: mlc

  • Samsung Begins Volume Production of 30-nm-class, 3-bit MLC NAND Flash Chips

    Samsung announced that it commenced the industry’s first volume production of 3-bit, multi-level-cell NAND flash chips using 30-nm-class process technology at the end of November.

    The chips will be used in NAND flash modules accompanied by Samsung 3-bit NAND controllers to initially produce 8 GB microSD cards.

    According to Samsung, three-bit MLC NAND increases the efficiency of NAND data storage by 50 percent over today’s pervasive 2-bit MLC NAND chips and provides consumers with effective NAND-based storage that can be applied to USB flash drives in addition to a range of micro SD cards.

    The company claims mass production of 30nm 3-bit NAND will significantly raise the portion of NAND flash memory production devoted to high densities (32Gb and above), designed to accommodate increased video usage.

    Samsung also announced other NAND advancements – the industry’s first mass production of its 30-nm-class, 32 Gb, MLC NAND memory with an asynchronous DDR interface.

    The company said it began shipping initial production of its DDR NAND to major OEMs at the end of November.

    DDR NAND is expected to raise the read performance of mobile devices requiring high-speeds and large amounts of storage space. Samsung’s new DDR MLC NAND chip, which reads at 133 Mbps would replace single data rate MLC NAND, which has an overall read performance of 40Mbps.

    Use of 30nm-class DDR NAND enables premium memory cards to register 60Mbps read speeds, at least a 300 percent performance gain compared to SDR NAND-based memory cards with an average 17Mbps read speed.

    According to market research firm Gartner Dataquest, the global NAND flash memory market is forecast to be worth US$13.8 billion in 2009 and reach US$23.6 billion by 2012.

  • Intel Advances Roadmap to Double SSD Capacity


    Intel is to implement the projected doubling of its SSD capacities earlier than expected – possibly as soon as next month.

    The current X18-M and X25-M solid-state drives (SSDs) use a 50nm process and have 80GB and 160GB capacities with 2-bit multi-level cell (MLC) technology.

    A single level cell (SLC) X25-E has faster I/O rates and comes in 32GB and 64GB capacities.

    In January, it was reported that Intel wanted to move to a smaller 34nm process and double the capacities with the 1.8-inch form factor X18-M and 2.5-inch form factor X25-M (M meaning Mainstream) moving to 160GB and 320GB capacities.

    This is now expected to take place, with the X25-E growing to 64GB and 128GB capacities.

    No information is available yet on pricing.

  • Hyperstone Launches New F4 Flash Memory Controller


    Hyperstone has introduced a new F4 Flash Memory Controller for high performance CompactFlash Cards(CFC) and Solid State Disks(SSD), writes Vanitha Vaidialingam for storage-biz.news.

    The memory controllers are intended for embedding into firmware to provide high reliability, endurance and rigorous fail safe features for Single Level Cell(SLC) and Multi Level Cell(MLC) based Flash Memory Solutions.

    The design is based on Hyperstone 32 bit RISC core including instruction set extensions optimized for Flash handling.

    Hyperstone’s core architecture provides both fast RISC processors for data and control functions along with powerful DSP unit for efficient algorithm execution.

    The designs use less silicon and are more power efficient with minimum software complexity.

    The Flash Memory controllers are fully compliant with CompactFlash 3.0 and compatible to 4.1 specifications.

    The controllers also offer Fast ATA supporting PIO mode 6, MDMA mode 4, UDMA mode 4 in True-IDE mode and UDMA 5 possible in fixed board implementations.

    They are designed to sustained read up to 50 MB/s and random read up to 40 MB/s; sustained write exceeding 40 MB/s with interleaving and random write up to 9 MB/s.

    The controllers have two Direct Flash Access(DFA) channels including Sector Buffers and interleaving capabilities. They support connections of up to 16 flash memory chip enables at the rate of eight per channel.

    The Error Correcting code is capable of correcting 4 symbols in a 512 bytes sector with additional CRC.

    The rate of data transfer is up to 80 MB sector.

    Host data transfer rate in UDMA mode 4 is 66 MB sector; in PIO mode 6, it is 512 bytes sector with additional CRC. Data transfer in the MDMA mode 4 is 25 MB sector.