The memory controllers are intended for embedding into firmware to provide high reliability, endurance and rigorous fail safe features for Single Level Cell(SLC) and Multi Level Cell(MLC) based Flash Memory Solutions.
The design is based on Hyperstone 32 bit RISC core including instruction set extensions optimized for Flash handling.
Hyperstone’s core architecture provides both fast RISC processors for data and control functions along with powerful DSP unit for efficient algorithm execution.
The designs use less silicon and are more power efficient with minimum software complexity.
The Flash Memory controllers are fully compliant with CompactFlash 3.0 and compatible to 4.1 specifications.
The controllers also offer Fast ATA supporting PIO mode 6, MDMA mode 4, UDMA mode 4 in True-IDE mode and UDMA 5 possible in fixed board implementations.
They are designed to sustained read up to 50 MB/s and random read up to 40 MB/s; sustained write exceeding 40 MB/s with interleaving and random write up to 9 MB/s.
The controllers have two Direct Flash Access(DFA) channels including Sector Buffers and interleaving capabilities. They support connections of up to 16 flash memory chip enables at the rate of eight per channel.
The Error Correcting code is capable of correcting 4 symbols in a 512 bytes sector with additional CRC.
The rate of data transfer is up to 80 MB sector.
Host data transfer rate in UDMA mode 4 is 66 MB sector; in PIO mode 6, it is 512 bytes sector with additional CRC. Data transfer in the MDMA mode 4 is 25 MB sector.